Low Power Adder Design For Use In Computation In-memory

نوع: Type: Thesis

مقطع: Segment: masters

عنوان: Title: Low Power Adder Design For Use In Computation In-memory

ارائه دهنده: Provider: Ali Akbarian

اساتید راهنما: Supervisors: Dr. Abbas Ramazani

اساتید مشاور: Advisory Professors:

اساتید ممتحن یا داور: Examining professors or referees: Dr. Mahdi Abbasi, Dr. Hatam Abdoli

زمان و تاریخ ارائه: Time and date of presentation: 2026

مکان ارائه: Place of presentation: سمینار مهندسی کامپیوتر

چکیده: Abstract: .Adders are fundamental building blocks in the design and implementation of modern processors. Meanwhile, understanding the memory architectures that enable in-memory computation has become a major research challenge. One of the key advantages of in-memory computing is its ability to efficiently handle large amounts of data. In conventional architectures, frequent data transfers between the central processing unit (CPU) and main memory lead to excessive data transfers, which lead to high energy consumption, increased power dissipation, and reduced performance. This inefficiency is particularly severe when applications are memory-dependent—for example, in the case of last-level cache misses—where data must be fetched from main memory at a rate that cannot maintain optimal performance and energy efficiency even with advanced cache hierarchies. The time and energy required to transfer data from memory to the computing units significantly limits system performance. To address this challenge, computations can be moved from the CPU to main memory at different granularities, from complex processing cores to simple computational units such as adders. By performing computations directly in memory, the data traffic between the CPU and memory is significantly reduced, leading to reduced energy and power consumption. Therefore, the main goal of this work is to achieve improved energy efficiency and reduced power consumption

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